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It is anticipated that the role will be split approximately 70% in designing CMOS IP blocks and CMOS top level design and 30% in the design of masks for internal processing of wafers within e2v. The specific tasks are:
- Full custom layout of CMOS IP blocks for wafers to be processed by external foundries.
- Layout verification and debug against design.
- Supporting of the design of image sensor: parasitic blocks extraction or proposing test case layout to evaluate parasitic for instance.
- Supporting interface with the external foundry as well as CAD team.
- Producing documentations for layout review and tapeout.
- Layout/design of masks for wafer processing within e2v
- Supporting the development of the design rules for e2v’s internal wafer processing
- Writing of layout reports for customers
- Participation in design reviews
- To participate in the continuous improvement of the design flow for space and Astronomy. To ensure that the right tools and methodology are put in place to satisfy the flow requirements.
- Protect our intellectual property and hence market position by identifying novel solutions for patent protection
- To contribute to the development of new technology building blocks to ensure that e2v can meet the needs of space customers in the future. This is the definition of new building blocks and, where appropriate, the layout design and manufacture of new building blocks.
To succeed in this role you must have:
- Knowledge of Cadence Open Access design tools including PVS
- Analogue layout
- Able to write documentation for internal use and customer.
In addition to the above experience it is expected that the candidate would be able to develop their expertise in the following areas with training/support from the existing team
- Understanding of the science and space business
- Understanding of the requirements to design masks for internal processing (for both CMOS and CCD imagers)
- Imaging including electro-optical performance
- CMOS process and radiation effects
- Top level floor planning and assembly
- Pixel CMOS technology
A good level of English both oral and written
-
It is anticipated that the role will be split approximately 70% in designing CMOS IP blocks and CMOS top level design and 30% in the design of masks for internal processing of wafers within e2v. The specific tasks are:
- Full custom layout of CMOS IP blocks for wafers to be processed by external foundries.
- Layout verification and debug against design.
- Supporting of the design of image sensor: parasitic blocks extraction or proposing test case layout to evaluate parasitic for instance.
- Supporting interface with the external foundry as well as CAD team.
- Producing documentations for layout review and tapeout.
- Layout/design of masks for wafer processing within e2v
- Supporting the development of the design rules for e2v’s internal wafer processing
- Writing of layout reports for customers
- Participation in design reviews
- To participate in the continuous improvement of the design flow for space and Astronomy. To ensure that the right tools and methodology are put in place to satisfy the flow requirements.
- Protect our intellectual property and hence market position by identifying novel solutions for patent protection
- To contribute to the development of new technology building blocks to ensure that e2v can meet the needs of space customers in the future. This is the definition of new building blocks and, where appropriate, the layout design and manufacture of new building blocks.
To succeed in this role you must have:
- Knowledge of Cadence Open Access design tools including PVS
- Analogue layout
- Able to write documentation for internal use and customer.
In addition to the above experience it is expected that the candidate would be able to develop their expertise in the following areas with training/support from the existing team
- Understanding of the science and space business
- Understanding of the requirements to design masks for internal processing (for both CMOS and CCD imagers)
- Imaging including electro-optical performance
- CMOS process and radiation effects
- Top level floor planning and assembly
- Pixel CMOS technology
A good level of English both oral and written
-
This role would ideally be suited to an experienced engineer with recent analogue and mixed-signal CMOS design experience looking for a new challenge.
Mixed Signal Design
- Participate to the feasibility study of new projects by providing design solutions and development time estimations.
- Designing analogue, mixed-signal (ADC) and full custom blocks for imaging (specification, architecture, schematic, outputting guidance for layout and review of layout, simulation, test strategy, robustness of the design).
- To ensure that designs are right first time or that only a metal fix is required if that has been defined in the programme plan.
- Ensure that newly design circuits have been designed for ease of testability.
- Support the test and characterization team.
Continuous Improvement
- To participate in the continuous improvement of the design flow for space and Astronomy.
To ensure that the right tools and methodology are put in place to satisfy the flow requirements.
Innovation
- Protect our intellectual property and hence market position by identifying novel solutions for patent protection
- To contribute to the design of new technology building blocks to ensure that e2v can meet the needs of space customers in the future.
ESSENTIAL EXPERIENCE/COMPETENCIES
Day to day “hands-on” experience of:
- Designing in CMOS technologies
- Use of design tools: Analogue simulation, Mixed simulation for top level verification.
- Supporting test and characterisation
Able to:
- Present justification of design options and choice made.
- Write Technical documentation for internal use, customer
A good level of English both oral and written.
-
This role would ideally be suited to an experienced engineer with recent analogue and mixed-signal CMOS design experience looking for a new challenge.
Mixed Signal Design
- Participate to the feasibility study of new projects by providing design solutions and development time estimations.
- Designing analogue, mixed-signal (ADC) and full custom blocks for imaging (specification, architecture, schematic, outputting guidance for layout and review of layout, simulation, test strategy, robustness of the design).
- To ensure that designs are right first time or that only a metal fix is required if that has been defined in the programme plan.
- Ensure that newly design circuits have been designed for ease of testability.
- Support the test and characterization team.
Continuous Improvement
- To participate in the continuous improvement of the design flow for space and Astronomy.
To ensure that the right tools and methodology are put in place to satisfy the flow requirements.
Innovation
- Protect our intellectual property and hence market position by identifying novel solutions for patent protection
- To contribute to the design of new technology building blocks to ensure that e2v can meet the needs of space customers in the future.
ESSENTIAL EXPERIENCE/COMPETENCIES
Day to day “hands-on” experience of:
- Designing in CMOS technologies
- Use of design tools: Analogue simulation, Mixed simulation for top level verification.
- Supporting test and characterisation
Able to:
- Present justification of design options and choice made.
- Write Technical documentation for internal use, customer
A good level of English both oral and written.
-
This role would ideally be suited to an experienced engineer with recent analogue and mixed-signal CMOS design experience looking for a new challenge.
Mixed Signal Design
- Participate to the feasibility study of new projects by providing design solutions and development time estimations.
- Designing analogue, mixed-signal (ADC) and full custom blocks for imaging (specification, architecture, schematic, outputting guidance for layout and review of layout, simulation, test strategy, robustness of the design).
- To ensure that designs are right first time or that only a metal fix is required if that has been defined in the programme plan.
- Ensure that newly design circuits have been designed for ease of testability.
- Support the test and characterization team.
Continuous Improvement
- To participate in the continuous improvement of the design flow for space and Astronomy.
- To ensure that the right tools and methodology are put in place to satisfy the flow requirements.
Innovation
- Protect our intellectual property and hence market position by identifying novel solutions for patent protection
- To contribute to the design of new technology building blocks to ensure that e2v can meet the needs of space customers in the future.
ESSENTIAL EXPERIENCE/COMPETENCIES
Day to day “hands-on” experience of:
- Designing in CMOS technologies
- Use of design tools: Analogue simulation, Mixed simulation for top level verification.
- Supporting test and characterisation
Able to:
- Present justification of design options and choice made.
- Write Technical documentation for internal use, customer
A good level of English both oral and written.
-
1)Customer support
1)Acceptance Test Protocol (ATP): defines, in agreement with all other engineering team, and the customer, the list of tests to be performed, and their limits
2)Documentation: creates and/or revises all internal and external document related with assembly, inspection and test
3)Has full traceability of all pre-production material and owns the inventory
4)Manages RMAs and drives the implementation of corrective actions to minimize reoccurrence
2)Test platform and final test (FT) development:
1)Defines requirements related to pre-production and production during the development phase, including custom test/requirements
2)Ensures that the hardware required for final test is in place and that it allows for stable and repeatable measurements of the sensor’s performance.
3)Defines the appropriate quantity of test platforms, sockets and other hardware (light sources…) required to support the production and the pre-production activities efficiently
4)Develops the FT program according to best known methods, known failure mechanism, sensor’s architecture, ATP and customer specifications
3)Cross-functional development
1)Works with other groups at Teledyne-Anafocus to manage the transition from engineering to pre-production and the ramp-up to production
4)Pre-production and ramp up
1)Defines the qualification plan based on costs, schedule, forecast and customer requirements
2)Drives all qualification activities, including testing and selection of the samples required
3)Select the appropriate subcontactors (whenever possible) and drives the interaction
4)Drives the Failure Analysis (FA) process when needed
5)Control stock against forecast and customer needs
6)Suggest improvements to the PM at any level (HW, SF, ATP…)
7)Develops the tool to maximize yield in assembly (for example, a SW GUI)
5)Wafer sort (WS) develop
1)Defines wafer sort requirements in agreement with the PM, specification, ATP
2)Oversees the implementation and release to production
6)Monitors the yield continuously and highlights ways to improve it, or weakest links, both internal and related to subcontractors
7)Monitors the test data (both WS and FT) and suggest periodic reviews of the limits with customers
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- Learn the architectures and operations of the sensor to characterize.
- Develop the control libraries of the sensor test system.
- Define the characterization plan in collaboration with the Design Technical Leader and the Project Coordinator.
- Responsible for debugging, running functional tests, and acquiring electro-optical measurements, as defined in the characterization plan.
- Analyze and report the results of the measures in a report.
- Provide technical support to customer support and the production team through research and debugging of possible deviations in the behavior and performance of the systems reported by users.